The present invention relates, in general, to electronics, and more particularly, to semiconductor packages, structures thereof, and methods of forming semiconductor packages.
In the past, packaged power semiconductor devices utilized various conductive interconnect techniques to electrically connect a power semiconductor die to conductive leads of a packaged device. In discrete power semiconductor devices, such as discrete insulated-gate field effect transistor (IGFET) semiconductor devices, manufacturers have utilized conductive ribbons and bonded wire or wirebond interconnects (including multiple wirebonds per electrode) for connecting current carrying electrodes on the power semiconductor device to the conductive leads of the package. However, these types of interconnects have not been able to provide sufficient current carrying capability as required in certain higher power devices.
As an alternative interconnect structure, manufacturers have used larger sized conductive clips as a replacement to ribbons and wirebonds to connect current carrying electrodes on the power semiconductor device to the conductive leads of the package. One problem with present semiconductor packages and methods using conductive clips is an insufficient ability to inspect conductive solder coverage between a main surface of the conductive clip and a main surface of the semiconductor die where the conductive clip is attached. In the past, manufacturers have used X-Ray examination after a solder reflow step to detect voiding defects; however, X-Ray examination is not sufficient for detecting other issues, such as actual solder coverage. Another past approach to address solder coverage for conductive clips has relied on process control methods, where trial and error has been used to characterize solder attach processes and to establish appropriate process windows. One problem with this approach is that it has had to rely on varying solder stencil thickness, evaluating different types of solder pastes, and varying the amount solder dispensed to establish the applicable process windows. Another problem with this approach is that it has required multiple process runs through assembly, which takes time and consumes materials, which adds costs. Further, this past approach has relied on X-Ray examination and electrical testing, but these approaches have not been able to detect every condition relevant to assuring optimum solder coverage.
Accordingly, it is desirable to have a structure and a method of forming a packaged semiconductor device that addresses the issues noted previously as well as others. It is also desirable for the structure and method to accommodate existing manufacturing flows and evaluation techniques.
The following discussion presents various aspects of the present disclosure by providing examples thereof. Such examples are non-limiting, and thus the scope of various aspects of the present disclosure should not necessarily be limited by any particular characteristics of the provided examples. In the following discussion, the phrases “for example,” “e.g.,” and “exemplary” are non-limiting and are generally synonymous with “by way of example and not limitation,” “for example and not limitation,” and the like.
For simplicity and clarity of the illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein, the term and/or includes any and all combinations of one or more of the associated listed items. In addition, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprises, comprising, includes, and/or including, when used in this specification, specify the presence of stated features, numbers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and/or groups thereof. It will be understood that, although the terms first, second, etc. may be used herein to describe various members, elements, regions, layers and/or sections, these members, elements, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one member, element, region, layer and/or section from another. Thus, for example, a first member, a first element, a first region, a first layer and/or a first section discussed below could be termed a second member, a second element, a second region, a second layer and/or a second section without departing from the teachings of the present disclosure. Reference to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment, but in some cases it may. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art, in one or more embodiments. Additionally, the term while means a certain action occurs at least within some portion of a duration of the initiating action. Unless specified otherwise, spatially relative terms, such as beneath, under, bottom, below, lower, above, top, upper, and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as below or beneath other elements or features would then be oriented above the other elements or features. Thus, the exemplary term below can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly. The use of word about, approximately or substantially means a value of an element is expected to be close to a state value or position. However, as is well known in the art there are always minor variances preventing values or positions from being exactly stated. Unless specified otherwise, as used herein the word over or on includes orientations, placements, or relations where the specified elements can be in direct or indirect physical contact. It is further understood that the embodiments illustrated and described hereinafter suitably may have embodiments and/or may be practiced in the absence of any element that is not specifically disclosed herein.